1. Field of the Invention
The present invention relates to a buffer circuit and to a tolerant buffer circuit capable of outputting two or more signal outputs of different high voltage levels, for example, in a general-purpose logic output circuit.
2. Description of Related Art
As miniaturization and more functionality by minute forming of the LSI (Large Scale Integration) proceed, various portable devices are being realized. Many of them are required to operate using lithium ion (Li+) batteries. In such portable devices, a system power supply LSI taking on power supply control needs to supply control signals for supplying power supply to many peripheral LSI's.
For this reason, a tolerant buffer for outputting a logic according to various voltage levels of the peripheral LSI becomes necessary for the system power LSI. Along with lowering of power supply voltages in recent years, their power ranges have been widening.
FIG. 8 is a circuit diagram of the tolerant buffer circuit for explaining a problem of the present invention. In the tolerant buffer circuit, control signals S1, S2 inside the LSI are inputted into it, and an output signal S3 to the outside of the LSI is outputted. Here, the control signal S1 is a signal that selects an output level when a high voltage (H: High) level is outputted from the output signal S3. Moreover, the control signal S2 is a signal that controls an output logic of the output signal S3. A power supply voltage VDDH and a power supply voltage VDDL are signal levels when a H level is outputted from the output signal S3. Here, the power supply voltage VDDH is a level higher than the power supply voltage VDDL.
The tolerant buffer circuit has inverter circuits P4, P8 controlled with a power supply voltage VDDH level, NAND circuits P5, P6 controlled with the power supply voltage VDDH level, a level shifter circuit P7 working between the power supply voltages VDDH and VDDL, PMOS transistors M109, M111, and an NMOS transistor M110.
When the control signal S2 is at a low voltage (L: Low) level, the output signal S3 becomes L level regardless of a logic of the control signal S1. When the control signal S2 is at H level and the control signal S1 is at H level, the output signal S3 becomes the power supply voltage VDDH level. On the other hand, when the control signal S2 is at H level and the control signal S1 is at L level, the output signal S3 becomes a power supply voltage VDDL level.
When the control signals S1, S2 are at H level, since the output signal S3 becomes the power supply voltage VDDH level, it is necessary to make a backgate of the PMOS transistor M109 become a level equal to that of the power supply voltage VDDH. Therefore, the power supply voltage, VDDH is fed to the backgate of the PMOS transistor M109. Incidentally, Japanese Patent Application Laid Open No. Hei3(1991)-185923 (Patent Document 1) discloses a tolerant buffer circuit similar with that of FIG. 8.